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1 ltc1411 1411f single supply 14-bit 2.5msps adc the ltc ? 1411 is a 2.5msps sampling 14-bit a/d con- verter in a 36-pin ssop package, which typically dissi- pates only 195mw from a single 5v supply. this device comes complete with a high bandwidth sample-and- hold, a precision reference, programmable input ranges and an internally trimmed clock. the adc can be powered down with either the nap or sleep mode for low power applications. the ltc1411 converts either differential or single-ended inputs and presents data in 2s complement format. maximum dc specs include 2lsb inl and 14-bit no missing code over temperature. outstanding dynamic performance includes 80db s/(n + d) and 90db thd at 100khz input frequency. the ltc1411 has four programmable input ranges se- lected by two digital input pins, pga0 and pga1. this provides input spans of 1.8v, 1.27v, 0.9v and 0.64v. an out-of-the-range signal together with the d13 (msb) will indicate whether a signal is over or under the adcs input range. a simple conversion start input and a data ready signal ease connections to fifos, dsps and micro- processors. n sample rate: 2.5msps n 80db s/(n + d) and 90db thd at 100khz f in n single 5v operation n no pipeline delay n programmable input ranges n low power dissipation: 195mw (typ) n true differential inputs reject common mode noise n out-of-range indicator n internal or external reference n sleep (1 m a) and nap (2ma) shutdown modes n 36-pin ssop package , ltc and lt are registered trademarks of linear technology corporation. n telecommunications n high speed data acquisition n digital signal processing n multiplexed data acquisition systems n spectrum analysis n imaging systems otr d13 ognd dvp ov dd control logic 2.5v bandgap reference internal clock 14-bit adc output drivers refout 14 + pga0 pga1 convst dgnd 1411 bd a in + a in nap slp avm 7, 8, 9 3 refin 2k 5k 5k 2 1 32 33 34 35 36 11 agnd 31 26 busy 27 d0 25 12 28 29 30 4 refcom1 5 refcom2 6 x1.62/ x1.15 avp 10 features descriptio u applicatio s u block diagra w input frequency (khz) 10 38 s/(n + d) (db) effective bits 50 62 100 1000 10000 1411 ta02 26 14 86 74 32 44 56 20 80 68 10 14 12 13 11 s/(n + d) and effective bits vs input frequency
2 ltc1411 1411f avp = dvp = ov dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................. 6v analog input voltage (note 3) ... C 0.3v to (v dd + 0.3v) digital input voltage (note 4) .................. C 0.3v to 10v digital output voltage ............... C 0.3v to (v dd + 0.3v) power dissipation .............................................. 500mw operating temperature range ltc1411c ............................................... 0 c to 70 c ltc1411i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number LTC1411CG ltc1411ig 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view g package 36-lead plastic ssop 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 slp nap pga0 pga1 convst dgnd dvp ov dd ognd busy otr d0 d1 d2 d3 d4 d5 d6 a in + a in refout refin refcom1 refcom2 agnd1 agnd2 agnd3 avp avm d13 (msb) d12 d11 d10 d9 d8 d7 t jmax = 125 c, q ja = 95 c/ w temperature range, otherwise specifications are t a = 25 c. (notes 5, 6) the l denotes specifications which apply over the full operating parameter conditions min typ max units resolution (no missing codes) l 14 bits integral linearity error (note 7) l 2 lsb offset error (note 8) 16 lsb l 24 lsb full-scale error external reference = 2.5v 60 lsb full-scale tempco i out(ref) = 0 15 ppm/ c accuracy ic dy u w a t a = 25 c (note 5) symbol parameter conditions min typ max units s/(n + d) signal-to-noise plus distortion ratio 100khz input signal 80.0 db 500khz input signal 77.5 db thd total harmonic distortion 100khz input signal, up to 5th harmonic C 90 db 500khz input signal, up to 5th harmonic C 82 db peak harmonic or spurious noise 100khz input signal 90 db 500khz input signal 82 db full linear bandwidth s/(n + d) 3 74db 1.0 mhz transition noise 0.66 lsb rms absolute axi u rati gs w ww u package/order i for atio uu w co verter characteristics u consult ltc marketing for parts specified with wider operating temperature ranges.
3 ltc1411 1411f symbol parameter conditions min typ max units v in analog input range (note 9) (a in + ) C (a in C ), pga0 = pga1 = 5v 1.8 v (a in + ) C (a in C ), pga0 = 5v, pga1 = 0v 1.27 v (a in + ) C (a in C ), pga0 = 0v, pga1 = 5v 0.9 v (a in + ) C (a in C ), pga0 = pga1 = 0v 0.64 v common mode input range a in + or a in C 0v dd v c in analog input capacitance between conversions (sample mode) 10 pf during conversions (hold mode) 4 pf t acq sample-and-hold acquisition time 100 ns t ap sample-and-hold aperture delay time 7 ns t jitter sample-and-hold aperture delay time jitter 1 ps rms cmrr analog input common mode rejection ratio 0v < (a in C = a in + ) < v dd 62 db input leakage current (pins 1, 2) 0.1 m a parameter conditions min typ max units v ref output voltage i out = 0 2.480 2.500 2.520 v v ref output tempco i out = 0 15 ppm/ c v ref line regulation 4.75v v dd 5.25v 0.01 lsb/ v v ref load regulation 0 ? i out ? 1ma 2 lsb/ma refcom2 output voltage i out = 0, pga0 = pga1 = 5v 4.05 v refin input current refin = external reference 2.5v 250 m a symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd , except slp, nap (note 11) l 10 m a c in digital input capacitance 2pf v oh high level output voltage v dd = 4.75v, i o = C 10 m a 4.75 v v dd = 4.75v, i o = C 200 m a l 4.0 v v ol low level output voltage v dd = 4.75v, i o = 160 m a 0.05 v v dd = 4.75v, i o = 1.6ma l 0.10 0.4 v i source output source current v out = 0v C 10 ma i sink output sink current v out = v dd 10 ma the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. (note 5) symbol parameter conditions min typ max units v dd supply voltage (note 9) 4.75 5.25 v i dd supply current l 39 65 ma nap mode nap = 0v (note 11) 2 ma sleep mode slp = 0v 1 m a p d power dissipation l 195 325 mw nap mode nap = 0v 10 mw sleep mode slp = 0v 5 m w the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. (note 5) t a = 25 c (note 5) t a = 25 c (note 5) a alog i put u u i ter al refere ce characteristics uu u digital i puts a d digital outputs u u power require e ts w u
4 ltc1411 1411f ti i g characteristics w u range, otherwise specifications are t a = 25 c. (notes 5) (see figures 11a, 11b) the l denotes specifications which apply over the full operating temperature symbol parameter conditions min typ max units f sample(max) maximum sampling frequency (note 9) l 2.5 mhz t conv conversion time l 250 350 ns t acq acquisition time 100 ns t 0 slp - to convst wake-up time 10 m f bypass capacitor at refcom2 pin 210 ms t 1 nap - to convst wake-up time 250 ns t 2 convst low time (note 10) l 20 ns t 3 convst to busy delay c l = 25pf 12 ns t 4 data ready after busy - 7ns t 5 convst high time (note 10) l 20 ns t 6 aperture delay of sample-and-hold 7 ns note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd, ognd, avm and agnd wired together unless otherwise noted. note 3: when these pin voltages are taken below agnd or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma without latchup. note 4: when these pin voltages are taken below agnd, they will be clamped by internal diodes. this product can handle input currents greater than 100ma below agnd without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, pga1 = pga0 = 5v, f sample = 2.5mhz at 25 c and t r = t f = 5ns unless otherwise specified. note 6: linearity, offset and full-scale specifications apply for a single- ended a in + input with a in C tied to an external 2.5v reference voltage. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: bipolar offset is the offset voltage measured from C 0.5lsb when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. note 9: recommended operating conditions. note 10: the falling convst edge starts a conversion. if convst returns high at a critical point during the conversion it can create small errors. for best performance ensure that convst returns high within 20ns after conversion start of after busy rises. note 11: slp and nap have an internal pull-down so the pins will draw approximately 7 m a when tied high and less than 1 m a when tied low. typical perfor a ce characteristics uw signal-to-noise ratio vs input frequency input frequency (khz) 10 38 s/(n + d) (db) 50 62 100 1000 10000 1411 g01 26 14 86 74 32 44 56 20 80 68 input frequency (khz) 10 38 snr (db) 50 62 100 1000 10000 1411 g02 26 14 86 74 32 44 56 20 80 68 input frequency (khz) 10 ?0 distortion (db) ?0 ?0 100 1000 10000 1411 g03 ?00 ?10 0 ?0 ?0 ?0 ?0 ?0 ?0 2nd 3rd thd s/(n + d) vs input frequency distortion vs input frequency
5 ltc1411 1411f typical perfor a ce characteristics uw input frequency (khz) 10 ?0 distortion (db) ?0 ?0 100 1000 10000 1411 g04 ?00 ?10 0 ?0 ?0 ?0 ?0 ?0 ?0 spurious free dynamic range vs input frequency s/(n + d) vs input frequency and amplitude integral nonlinearity vs output code differential nonlinearity vs output code input frequency (khz) 10 38 sinad (db) 50 62 100 1000 10000 1411 g05 26 14 86 74 32 44 56 20 80 68 0db 20db 40db output code 0 ?.0 inl (lsb) 0.8 0.4 0.2 0 1.0 0.4 4096 8192 1411 g07 0.6 0.6 0.8 0.2 12288 16384 output code 0 ?.0 dnl (lsb) 0.8 0.4 0.2 0 1.0 0.4 4096 8192 1411 g08 0.6 0.6 0.8 0.2 12288 16384 supply current vs temperature temperature ( c) ?0 45 44 43 42 41 40 39 38 37 36 35 supply current (ma) ?5 0 25 50 1411 g11 75 100 v dd = 5v supply current vs supply voltage v dd (v) 4.5 31.5 supply current (ma) 34.0 36.5 39.0 41.5 44.0 46.5 t a = 25 c 4.75 5.0 5.25 5.5 1411 g12 histogram for 4096 conversions code 3500 3000 2500 2000 1500 1000 500 0 01 1411 g13 ? counts 4096 points fft plot (100khz) input frequency (khz) 0 ?0 ?0 0 1411 g14 ?0 ?00 ?20 ?40 ?0 amplitude (db) sinad = 78.8db sfdr = 95db f sample = 2.5mhz f in = 100khz 1000 250 500 750 1250
6 ltc1411 1411f typical perfor a ce characteristics uw acquisition time vs source resistance 4096 points fft plot (1mhz) frequency (khz) 0 ?0 ?0 0 1000 1411 g15 ?0 ?0 250 500 750 1250 ?00 ?20 ?40 amplitude (db) sinad = 75db sfdr = 81db f sample = 2.5mhz f in = 1mhz source resistance ( ) 1 acquisition time ( s) 1 10 10000 1411 g16 0.1 0.01 10 100 1000 100000 100 a in + (pin 1): positive analog input. the adc converts the difference voltage between a in + and a in C with program- mable input ranges of 1.8v, 1.27v, 0.9v and 0.64v depending on pga selection. a in + has common mode range between 0v and v dd . a in C (pin 2): negative analog input. this pin can be tied to the refout pin of the adc or tied to an external dc voltage. this voltage is also the bipolar zero for the adc. a in C has common mode range between 0v and v dd . refout (pin 3): 2.5v reference output. bypass to agnd1 with a 22 m f tantalum capacitor if refout is tied to a in C . no capacitor is needed if the external reference is used to drive a in C . refin (pin 4): reference buffer input. this pin can be tied to refout or to an external reference if more precision is required. refcom1 (pin 5): noise reduction pin. put a 10 m f bypass capacitor at this pin to reduce the noise going into the reference buffer. refcom2 (pin 6): 4.05v reference compensation pin. bypass to agnd1 with a 10 m f tantalum capacitor in parallel with a 0.1 m f ceramic. uu u pi fu ctio s agnd (pins 7 to 9): analog ground. agnd1 is the ground for the reference. agnd2 is the ground for the comparator and agnd3 is the ground for the remaining analog circuitry. avp (pin 10): 5v analog power supply. bypass to agnd with a 10 m f tantalum capacitor. avm (pin 11): analog and digital substrate pin. tie this pin to agnd. d13 to d0 (pins 12 to 25): digital data outputs. d13 is the msb (most significant bit). otr (pin 26): out-of-the-range pin. this pin can be used in conjunction with d13 to determine if a signal is less than or greater than the analog input range. if d13 is low and otr is high, the analog input to the adc exceeds the maximum voltage of the input range. busy (pin 27): busy output. converter status pin. it is low during conversion. ognd (pin 28): digital ground for output drivers (data bits, otr and busy). ov dd (pin 29): 3v or 5v digital power supply for output drivers (data bits, otr and busy). bypass to ognd with a 10 m f tantalum capacitor.
7 ltc1411 1411f dvp (pin 30): 5v digital power supply pin. bypass to ognd with a 10 m f tantalum capacitor. dgnd (pin 31): digital ground. convst (pin 32): conversion start signal. this active low signal starts a conversion on its falling edge. pga1, pga0 (pins 33, 34): logic inputs for program- mable input range. this adc has four input ranges (or four refcom2 voltages) controlled by these two pins. for the logic inputs applied to pga0 and pga1, the following summarizes the gain levels and the analog input range with a in C tied to 2.5v. uu u pi fu ctio s table 1. input spans for ltc1411 input refcom2 pga0 pga1 level span voltage 5v 5v 0db 1.8v 4v 5v 0v C 3db 1.28v 2.9v 0v 5v C 6db 0.9v 2v 0v 0v C 9db 0.64v 1.45v nap (pin 35): nap input. driving this pin low will put the adc in the nap mode and will reduce the supply current to 2ma and the internal reference will remain active. slp (pin 36): sleep input. driving this pin low will put the adc in the sleep mode and the adc draws less than 1 m a of supply current. wu u u typical co ectio diagra otr 5v or 3v d13 ognd ov dd control logic 2.5v bandgap reference internal clock 14-bit adc output drivers refout 14 + pga0 pga1 convst dgnd 1411 ta01 a in + a in avp dvp 5v nap slp + avm 7, 8, 9 3 refin 22 f* 10 f 10 f 2k 5k 5k 2 1 32 33 34 35 36 11 agnd *a 22 f capacitor is needed if refout is used to drive a in 31 26 busy 27 d0 25 12 28 29 4 refcom1 5 refcom2 6 + 30 10 + + + x1.62/ x1.15
8 ltc1411 1411f test circuits load circuits for access timing load circuits for output float delay 1k (a) hi-z to v oh and v ol to v oh c l 1k 5v dn dn (b) hi-z to v ol and v oh to v ol c l 1411 tc01 1k (a) v oh to hi-z c l 1k 5v dn dn (b) v ol to hi-z c l 1411 tc02 applicatio s i for atio wu uu conversion details the ltc1411 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel output. the adc is complete with a precision reference, internal clock and a programmable input range. the device is easy to interface with microprocessors and dsps. (please refer to the digital interface section for the data format.) conversions are started by a falling edge on the convst input. once a conversion cycle has begun, it cannot be restarted. between conversions, the adc acquires the analog input in preparation for the next conversion. in the acquire phase, a minimum time of 100ns will provide enough time for the sample-and-hold capacitors to ac- quire the analog signal. during the conversion, the internal differential 14-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). the input is successively compared with the binary weighted charges supplied by the differential capacitive dac. bit decisions are made by a high speed comparator. at the end of a conversion, the dac output balances the analog input (a in + C a in C ). the sar contents (a 14-bit data word) which represents the difference of a in + and a in C are loaded into the 14-bit output latches. dynamic performance the ltc1411 has excellent high speed sampling capabil- ity. fft (fast fourier transform) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algo- rithm, the adcs spectral content can be examined for frequencies outside the fundamental. figure 2a shows a typical ltc1411 fft plot. signal-to-noise the signal-to-(noise + distortion) ratio [s/n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from the above dc and below half the sampling frequency. figure 2a shows a typical spectral content with a 2.5mhz sampling rate and a 100khz input. the dynamic performance holds well to higher input frequencies (see figure 2b). figure 1. simplified block diagram otr d13 ognd dvp ov dd control logic internal clock 14-bit adc output drivers 14 + pga0 pga1 convst dgnd 1411 f01 a in + a in nap slp 2 1 32 33 34 35 36 31 26 busy 27 d0 25 12 28 29 30 avp 10
9 ltc1411 1411f effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to the s/(n + d) by the equation: enob s = [s/(n + d) C 1.76]/6.02 where s/(n + d) is expressed in db. at the maximum sampling rate of 2.5mhz the ltc1411 maintains good enobs up to the nyquist input frequency of 1.25mhz. refer to figure 3. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental applicatio s i for atio wu uu input frequency (khz) 0 ?0 ?0 0 1411 g14 ?0 ?00 ?20 ?40 ?0 amplitude (db) sinad = 78.8db sfdr = 95db f sample = 2.5mhz f in = 100khz 1000 250 500 750 1250 figure 2a. ltc1411 nonaveraged, 4096 point fft, input frequency = 100khz itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd vvv v v n = +++? 20 2 2 3 2 4 22 1 log where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. thd vs input frequency is shown in figure 4. the ltc1411 has good distortion performance up to the nyquist frequency and beyond. frequency (khz) 0 ?0 ?0 0 1000 1411 g15 ?0 ?0 250 500 750 1250 ?00 ?20 ?40 amplitude (db) sinad = 75db sfdr = 81db f sample = 2.5mhz f in = 1mhz figure 2b. ltc1411 4096 point fft, input frequency = 1mhz figure 3. effective bits and signal/(noise + distortion) vs input frequency input frequency (khz) 10 38 s/(n + d) (db) effective bits 50 62 100 1000 10000 1411 ta02 26 14 86 74 32 44 56 20 80 68 10 14 12 13 11 figure 4. distortion vs input frequency input frequency (khz) 10 ?0 distortion (db) ?0 ?0 100 1000 10000 1411 g03 ?00 ?10 0 ?0 ?0 ?0 ?0 ?0 ?0 2nd 3rd thd
10 ltc1411 1411f the sampling capacitor, choose an amplifier that has a low output impedance (<100 w ) at the closed-loop bandwidth frequency. for example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50mhz, then the output impedance at 50mhz must be less than 100 w . the second requirement is that the closed-loop bandwidth must be greater than 40mhz to ensure adequate small- signal settling for full throughput rate. if slower op amps are used, more settling time can be provided by increasing the time between conversions. the best choice for an op amp to drive the ltc1411 will depend on the application. generally applications fall into two categories: ac applications where dynamic specifica- tions are most critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the ltc1411. more detailed information is available in the linear technology databooks and on the linearview tm cd-rom. lt ? 1227: 140mhz video current feedback amplifier. 10ma supply current. 5v to 15v supplies. low noise. good for ac applications. lt1395: 400mhz current feedback amplifier. single 5v or 5v supplies. good for ac applications. lt1800: 80mhz, 25v/ m s low power rail-to-rail input and output precision op amp. specified at 3v, 5v and 5v supplies. excellent dc performance. peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in db relative to the rms value of a full- scale input signal. full-power and full-linear bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is re- duced by 3db for a full-scale input signal. the full-linear bandwidth is the input frequency at which the s/(n + d) has dropped to 74db (12 effective bits). the ltc1411 has been designed to optimize input bandwidth, allowing the adc to undersample input signals with fre- quencies above the converters nyquist frequency. the noise floor stays very low at high frequencies; s/(n + d) becomes dominated by distortion at frequencies far be- yond nyquist. driving the analog input the differential analog inputs of the ltc1411 are easy to drive. the inputs may be driven differentially or as a single- ended input (i.e., the a in C input is tied to a fixed dc voltage such as the refout pin of the ltc1411 or an external source). figure 1 shows a simplified block diagram for the analog inputs of the ltc1411. the a in + and a in C are sampled at the same instant. any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. the inputs draw only one small current spike while charg- ing the sample-and-hold capacitors at the end of conver- sion. during conversion, the analog inputs draw only a small leakage current. if the source impedance of the driving circuits is low, then the ltc1411 inputs can be driven directly. more acquisition time should be allowed for a higher impedance source. figure 5 shows the acqui- sition time versus source resistance. choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifier from charging applicatio s i for atio wu uu source resistance ( ) 1 acquisition time ( s) 1 10 10000 1411 g16 0.1 0.01 10 100 1000 100000 100 figure 5. acquisition time vs source resistance linearview is a trademark of linear technology corporation.
11 ltc1411 1411f lt6203: dual 100mhz, low noise, low power op amp. specified at 3v, 5v and 5v supplies. 1.9nv/ ? hz noise voltage. programmable input range the ltc1411 has two logic input pins (pga0 and pga1) that are used to select one of four analog input ranges. these input ranges are set by changing the reference voltage that is applied to the internal dac of the adc (refcom2). for the 0db setting the internal dac sees the full reference voltage of 4v. the analog input range is 0.7v to 4.3v with a in C = 2.5v. this corresponds to an input span of 1.8v with respect to the voltage applied to a in C . for the C 3db setting the internal reference is reduced to 0.707 ? 4v = 2.9v. likewise the input span is reduced to 1.28v. the following table lists the input span with respect to a in C for the different pga0 and pga1 settings. table 1. input spans for ltc1411 input refcom2 pga0 pga1 level span voltage 5v 5v 0db 1.8v 4v 5v 0v C 3db 1.28v 2.9v 0v 5v C 6db 0.9v 2v 0v 0v C 9db 0.64v 1.45v when changing from one input span to another, more time is needed for the refcom2 pin to reach the correct level because the bypass capacitor on the pin needs to be charged or discharged. figure 6 shows the recommended capaci- tors at the refcom1 and refcom2 pins (10 m f each). when C 6db or C 9db is selected, the voltage at refcom1 (see figure 2) must first settle before refcom2 reaches the correct level. the typical delay is about 700ms. when the refcom2 level is changed from 2.9v to 4v (changing pga setting from C 3db to 0db), the typical delay is 0.6ms. however, if the voltage at refcom2 is changed from 4v to 2.9v (changing pga setting from 0db to C 3db) only a 60 m a sink current is present to discharge the 10 m f bypass capacitor. in this case, the delay will be 11ms. internal reference the ltc1411 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500v. if this refout pin is used to drive the a in C pin, a 22 m f tantalum bypass capacitor is required and this refout voltage sets the bipolar zero for the adc. the refin pin is connected to the reference buffer through a 2k resistor and two pga switches. the refin pin can be connected to refout directly or to an external reference. figure 6 shows the reference and buffer structure for the ltc1411. the input to the reference buffer is either refin or 1/2 of refin depending on the pga selection. the refcom1 pin bypassed with a 10 m f tantalum capacitor helps reduce the noise going into the buffer. the reference buffer has a gain of 1.62 or 1.15 (depends on pga selection). it is compensated at the refcom2 pin with a 10 m f tantalum capacitor. the input span of the adc is set by the output voltage of this refcom2 voltage. for a 2.5v input at the refin pin, the refcom2 will have 4v output for pga1 = pga0 = 5v and the adc will have a span of 3.6v. applicatio s i for atio wu uu figure 6. reference structure for the ltc1411 for pga1 = pga0 = 5v refcom2 10 f 1411 f06 refcom1 refin* refout 10 f this pin can be tied to refout or an external source a 22 f capacitor is needed if refout is used to drive a in * ** 22 f** 2k 5k 5k 2.5v bandgap reference x1.62
12 ltc1411 1411f figure 7 shows a typical reference, the lt1019a-2.5 connected to the ltc1411. this will provide an improved drift (equal to the maximum 5ppm/ c of the lt1019a-2.5). by driving the slp pin low for sleep mode, the adc shuts down to less than 1 m a. after release from the sleep mode, the adc needs 210ms (10 m f bypass capacitor on the refcom2 pin) to wake up. in nap mode, all the power is off except the internal refer- ence which is still active for the other external circuitry. in this mode the adc draws about 2ma instead of 39ma (for minimum power, the logic inputs must be within 600mv from the supply rails). the wake-up time from nap mode to active state is 250ns as shown in figure 9. board layout and bypassing wire wrap boards are not recommended for high resolu- tion or high speed a/d converters. to obtain the best performance from the ltc1411, a printed circuit board with a ground plane is required. layout for the printed circuit board should ensure that the digital and analog signal lines are separated as much as possible. in particu- lar, care should be taken not to run any digital track alongside an analog signal track. applicatio s i for atio wu uu figure 9. nap to convst wake-up timing figure 7. supplying a 2.5v reference voltage to the ltc1411 with the lt1019a-2.5 figure 8. overrange and underrange logic table 2. out-of-the-range truth table otr d13 (msb) analog input 0 0 in range 0 1 in range 1 0 overrange 1 1 underrange 3 2 6 4 1 2 4 7, 8, 9 input range: 0.7v to 4.3v 10 f 1411 f07 lt1019a-2.5 v in gnd v out 5v 5v ltc1411 a in + a in agnd refin digital interface the adc has a very simple digital interface with only one control input, convst. a logic low applied to the convst input will initiate a conversion. the adc presents digital data in 2s complement format with bipolar zero set by the voltage applied to the a in C pin. internal clock the internal clock is factory trimmed to achieve a typical conversion time of 260ns. with the typical acquisition time of 100ns, a throughput sampling rate of 2.5msps is guaranteed. out-of-the-range signal (otr) the ltc1411 has a digital output, otr, that indicates if an analog input signal is out of range. the otr remains low when the analog input is within the specified range. once the analog signal goes to the most negative input (1000 0000 0000 00) or 64lsb above the specified most positive input, otr will go high. by noring d13 (msb) and its complement with otr, overrange and underrange can be detected as shown in figure 8. table 2 is the truth table of the out-of-the-range circuit in figure 8. power shutdown (sleep and nap modes) the ltc1411 provides two shutdown features that will save power when the adc is inactive. otr d13 d13 ??for overrange u1-a u1-b u1-a, u1-b = 74hc or equivalent ??for underrange 1411 f08 t 1 nap convst 1411 f09
13 ltc1411 1411f applicatio s i for atio wu uu an analog ground plane separate from the logic system ground should be established under and around the adc. agnd1, 2, 3 (pins 7 to 9), avm (pin 11), dgnd (pin 31) and ognd (pin 28) and all other analog grounds should be connected to a single analog ground point. the refout, refcom1, refcom2 and avp should bypass to this analog ground plane (see figure 10). no other digital grounds should be connected to this analog ground plane. low impedance analog and digital power supply common returns are essential to low noise operation of the adc and the foil width for these tracks should be as wide as possible. timing and control conversion start is controlled by the convst digital input. the falling edge transition of the convst will start a conversion. once initiated, it cannot be restarted until the conversion is complete. converter status is indicated by the busy output. busy is low during a conversion. the digital output code is updated at the end of conversion about 7ns after busy rises, i.e., output data is not valid on the rising edge of busy. valid data can be latched with the falling edge of busy or with the rising edge of convst. in either case, the data latched will be for the previous conversion results. figures 11a and 11b are the timing diagrams for the ltc1411. 3v input/output compatible the ltc1411 operates on a 5v supply, which makes the device easy to interface to 5v digital systems. this device can also talk to 3v digital systems: the digital input pins (convst, nap and slp) of the ltc1411 recognize 3v or 5v inputs. the ltc1411 has a dedicated output supply pin (ov dd ) that controls the output swings of the digital output pins (d0 to d13, busy and otr) and allows the part to talk to either 3v or 5v digital systems. the output is twos complement binary. figure 12 is the input/output characteristics of the adc when a in C = 2.5v. the code transitions occur midway between successive integer lsb values (i.e., 0.5lsb, 1.5lsb, 2.5lsb... fs C 1.5lsb). the output code is scaled such that 1lsb = fs/16384 = 3.6v/16384 = 219.7 m v. offset and full-scale adjustment in applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. offset error must be adjusted before full-scale error. figure 13 shows the extra components required for full-scale error adjustment. zero offset is achieved by adjusting the offset applied to the a in C input. for zero offset error, apply 2.49989v (i.e., C 0.5lsb) at a in + and adjust r2 at the a in C input until the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. for full-scale adjustment, an input voltage of 4.29967v (fs C 1.5lsbs) is applied to a in + and r5 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11. figure 10. power supply grounding practice 1411 f10 a in + refcom2 ov dd dvp avp ltc1411 digital system analog input circuitry refcom1 5 2 6 29 31 ognd dgnd 28 avm 11 10 30 1 refin 4 refout 3 a in agnd1 7 agnd2 8 + agnd3 9
14 ltc1411 1411f applicatio s i for atio wu uu figure 12. ltc1411 bipolar transfer characteristics (2s complement) figure 11b. convst starts a conversion with a short active high pulse figure 11a. convst starts a conversion with a short active low pulse figure 13. offset and full-scale adjustment data n db13 to db0 data (n + 1) db13 to db0 data (n ?1) db13 to db0 convst busy 1411 f11a t 2 t conv t 3 t acq t 4 data (sample n) data (n ?1) db13 to db0 (sample n) convst busy 1411 f11b t conv t 3 t 5 t 4 data n db13 to db0 data (n + 1) db13 to db0 data t 3 t 5 t acq input voltage (v) 2.5v output code ? lsb 1411 f12 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fs/2 ?1lsb fs/2 1lsb = = = 219.7 v 3.6v 16384 fs 16384 r7 51 r1 51 r3 51k r2 10k offset adjust full-scale adjust 5v r4 100k r5 750 r6 100k 5v a in + a in ltc1411 refin 1411 f13
15 ltc1411 1411f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package descriptio g package 36-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) g36 ssop 0501 .13 ?.22 (.005 ?.009) 0 ?8 .55 ?.95 (.022 ?.037) 5.20 ?5.38** (.205 ?.212) 7.65 ?7.90 (.301 ?.311) 1234 5 6 7 8 9 10 11 12 14 15 16 17 18 13 12.67 ?12.93* (.499 ?.509) 25 26 22 21 20 19 23 24 27 28 29 30 31 32 33 34 35 36 1.73 ?1.99 (.068 ?.078) .05 ?.21 (.002 ?.008) .65 (.0256) bsc .25 ?.38 (.010 ?.015) millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale
16 ltc1411 1411f ? linear technology corporation 2001 lt/tp 0902 2k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts u typical applicatio otr 5v or 3v 14-bit output data d13 ognd ov dd control logic 2.5v bandgap reference programmable range differential inputs ( 0.64v to 1.8v) internal clock 14-bit adc output drivers refout 14 + pga0 pga1 convst dgnd 2.5mhz convert input input range selection 1411 ta03 a in + a in avp 5v dvp nap slp + avm 5v 7, 8, 9 3 refin 10 f 10 f 2k 5k 5k 2 1 32 33 34 35 36 11 agnd 31 26 busy 27 d0 25 12 28 29 4 refcom1 5 refcom2 6 + 30 10 + + x1.62/ x1.15 2.5msps 14-bit adc with programmable input range part number resolution speed comments 16-bit ltc1608 16 500ksps 2.5v input range, pin compatible with ltc1604 14-bit ltc1414 14 2.2msps 150mw, 81db sinad and 95db sfdr ltc1419 14 800ksps 150mw, 81.5db sinad and 95db sfdr ltc1744 14 50msps 1.5w, two modes: 77db snr or 90db sfdr 12-bit ltc1420 12 10msps 5v or 5v supply, 71db sinad and input pga ltc1412 12 3msps 150mw, 71db sinad and 84db thd ltc1402 12 2.2msps 90mw, serial interface, 16-lead ssop package ltc1405 12 5msps 115mw, 71.3db s/n+d, 85db sfdr ltc1410 12 1.25msps 150mw, 71.5db sinad and 84db thd ltc1415 12 1.25msps 55mw, single 5v supply

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